Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demand for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. As the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such features. Higher device densities, faster operating frequencies, and larger die sizes have created a need for a metal with lower resistivity than traditional aluminum to be used in interconnect structures. Copper materials with lower resistivity have been used for decades for its high conductivity. However, the small size features may result in increased resistivity of copper as line widths shrink below around 50 nm and approach the mean free path of electrons in copper (39 nm). The resistivity increase is caused by electron scattering at the surface of the line and at grain boundaries.
Conventional copper wire may also be damaged by electromigration when current density exceeds certain levels. Electromigration defects threaten the reliability of nanometer-size copper interconnects. Electromigration causes internal and external cavities that lead to wire failure. For example, electromigration may lead to increased electrical resistance or even an open circuit if a sufficiently large void forms within the copper interconnection.
Beyond the 5 nm technology node, new materials and schemes need to be implemented in Back-End-of-Line (BEOL) Interconnect to keep up with Moor's law. Convention metal based interconnects will likely not be effective. New disruptive materials and schemes are required. Silicide based interconnect are one among other potential paths being explored. Other candidates include carbon nano-tubes, graphene, optical and spintronics. It is believed that silicide based interconnects are a probable candidate to extend CMOS schemes beyond the 5 nm node. Carbon nano-tubes and graphene both require atomic switches to be implemented. Spintronics requires electron-spin based switches. Optical interconnect is cumbersome, requiring cooling systems and are larger, going against the scalability trend.
Silicides have been implemented in the semiconductor industry in Front-End-of-Line (FEOL) processes. FEOL processes can tolerate high thermal budgets over 650° C. BEOL processing cannot tolerate high thermal budgets due to low-k damage that occurs for temperatures higher than 400° C. Therefore, there is a need in the art for materials and methods for forming metal interconnections within the low thermal budget requirements of BEOL processes.